Abstract

We designed and implemented an extremely energyefficient hardware algorithm using adiabatic quantum-fluxparametron (AQFP) logic based on a hardware-algorithm known as the Collatz conjecture. The circuit is composed of mergers, oddeven check stages, path controllers, processing units, terminating stages, together with a feedback loop. This design is at least 3 orders of magnitude better in energy efficiency compared to rapidsingle-flux-quantum (RSFQ) designs and is superior to semiconductor-based designs even when including the power dissipation of a cryocooler.

Original languageEnglish
Title of host publication2015 15th International Superconductive Electronics Conference, ISEC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781467383486
DOIs
StatePublished - 2016 Jan 14
Event15th International Superconductive Electronics Conference, ISEC 2015 - Nagoya, Japan

Other

Other15th International Superconductive Electronics Conference, ISEC 2015
CountryJapan
CityNagoya
Period15/7/615/7/9

Fingerprint

Hardware
Superconducting materials
Energy efficiency
Energy dissipation
Semiconductor materials
Fluxes
Feedback
Controllers

Keywords

  • AQFP
  • Collatz conjecture
  • Digital simulation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Xu, Q., Yamanashi, Y., Yoshikawa, N., Ayala, C. L., Takeuchi, N., & Ortlepp, T. (2016). Design of an extremely energy-efficient hardware algorithm using adiabatic superconductor logic. In 2015 15th International Superconductive Electronics Conference, ISEC 2015. [7383446] Institute of Electrical and Electronics Engineers Inc.. DOI: 10.1109/ISEC.2015.7383446

Design of an extremely energy-efficient hardware algorithm using adiabatic superconductor logic. / Xu, Q.; Yamanashi, Y.; Yoshikawa, N.; Ayala, C. L.; Takeuchi, N.; Ortlepp, T.

2015 15th International Superconductive Electronics Conference, ISEC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7383446.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Xu, Q, Yamanashi, Y, Yoshikawa, N, Ayala, CL, Takeuchi, N & Ortlepp, T 2016, Design of an extremely energy-efficient hardware algorithm using adiabatic superconductor logic. in 2015 15th International Superconductive Electronics Conference, ISEC 2015., 7383446, Institute of Electrical and Electronics Engineers Inc., 15th International Superconductive Electronics Conference, ISEC 2015, Nagoya, Japan, 6-9 July. DOI: 10.1109/ISEC.2015.7383446
Xu Q, Yamanashi Y, Yoshikawa N, Ayala CL, Takeuchi N, Ortlepp T. Design of an extremely energy-efficient hardware algorithm using adiabatic superconductor logic. In 2015 15th International Superconductive Electronics Conference, ISEC 2015. Institute of Electrical and Electronics Engineers Inc.2016. 7383446. Available from, DOI: 10.1109/ISEC.2015.7383446

Xu, Q.; Yamanashi, Y.; Yoshikawa, N.; Ayala, C. L.; Takeuchi, N.; Ortlepp, T. / Design of an extremely energy-efficient hardware algorithm using adiabatic superconductor logic.

2015 15th International Superconductive Electronics Conference, ISEC 2015. Institute of Electrical and Electronics Engineers Inc., 2016. 7383446.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

@inbook{d3b0e6ac967d4a0a9d8536e05d01b597,
title = "Design of an extremely energy-efficient hardware algorithm using adiabatic superconductor logic",
keywords = "AQFP, Collatz conjecture, Digital simulation",
author = "Q. Xu and Y. Yamanashi and N. Yoshikawa and Ayala, {C. L.} and N. Takeuchi and T. Ortlepp",
year = "2016",
month = "1",
doi = "10.1109/ISEC.2015.7383446",
isbn = "9781467383486",
booktitle = "2015 15th International Superconductive Electronics Conference, ISEC 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - CHAP

T1 - Design of an extremely energy-efficient hardware algorithm using adiabatic superconductor logic

AU - Xu,Q.

AU - Yamanashi,Y.

AU - Yoshikawa,N.

AU - Ayala,C. L.

AU - Takeuchi,N.

AU - Ortlepp,T.

PY - 2016/1/14

Y1 - 2016/1/14

N2 - We designed and implemented an extremely energyefficient hardware algorithm using adiabatic quantum-fluxparametron (AQFP) logic based on a hardware-algorithm known as the Collatz conjecture. The circuit is composed of mergers, oddeven check stages, path controllers, processing units, terminating stages, together with a feedback loop. This design is at least 3 orders of magnitude better in energy efficiency compared to rapidsingle-flux-quantum (RSFQ) designs and is superior to semiconductor-based designs even when including the power dissipation of a cryocooler.

AB - We designed and implemented an extremely energyefficient hardware algorithm using adiabatic quantum-fluxparametron (AQFP) logic based on a hardware-algorithm known as the Collatz conjecture. The circuit is composed of mergers, oddeven check stages, path controllers, processing units, terminating stages, together with a feedback loop. This design is at least 3 orders of magnitude better in energy efficiency compared to rapidsingle-flux-quantum (RSFQ) designs and is superior to semiconductor-based designs even when including the power dissipation of a cryocooler.

KW - AQFP

KW - Collatz conjecture

KW - Digital simulation

UR - http://www.scopus.com/inward/record.url?scp=84968680188&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84968680188&partnerID=8YFLogxK

U2 - 10.1109/ISEC.2015.7383446

DO - 10.1109/ISEC.2015.7383446

M3 - Conference contribution

SN - 9781467383486

BT - 2015 15th International Superconductive Electronics Conference, ISEC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

ER -